Parallel Computing on Stampede
July 30 - 31, 2014 (Wednesday and Thursday)
8:30 a.m. to 5 p.m. CT, both days
J.J. Pickle Research Campus
10100 Burnet Rd
The Stampede supercomputer at the Texas Advanced Computing Center went into production in January 2013 and is the first system to deploy at scale the Intel Xeon Phi CoProcessor. Stampede provides nearly 10 petaflops of peak performance, and is the new flagship system of the US National Science Foundation's XSEDE Cyberinfrastructure. Stampede provides more than 100,000 cores and 2PF of Intel Xeon E5 "Sandy Bridge" processors, and an additional 7+ PF of Intel Xeon Phi CoProcessors.
In this tutorial, we will introduce the Stampede architecture, and cover how to achieve performance using both the conventional processors as well as the coprocessors.
You are encouraged to bring your own laptop. We have a limited number of laptops available for labs, first come, first served. If you choose to use your own laptop, please make sure that you have an SSH client.
Topics will include:
Stampede architecture overview
The Stampede user environment, including the batch system, compiler environment, application modules, etc.
MPI and OpenMP parallel programming
Hands-on exercises with Stampede.
Basic optimization and vector tuning on Stampede for Sandy Bridge and Xeon Phi Coprocessors (MICs)
Intel Xeon Phi Coprocessor (MIC) overview
Programming models for Sandy Bridge - MIC computing: native, symmetric and offload.
The labs will be available for remote users. However, we will not be able to assist remote users with problems during the lab.
Agenda - Parallel Computing on Stampede
The chat can be found here: https://tacc.etherpad.mozilla.org/7
Day 1 (Wednesday, July 30, 2014)
08:30-08:45 Welcome and Introductory Remarks
08:45-09:45 Introduction to Parallel Computing
10:00-11:00 User Environment
11:00-11:30 Lab 1 (User Environment)
12:30-13:50 OpenMP Programming
13:50-14:30 Lab 2 (OpenMP)
14:45-16:10 MPI Programming
16:10-17:00 Lab 3 - C Lab 3 - Fortran (MPI)
Day 2 (Thursday, July 31, 2014)
08:30-09:00 TACC Systems Overview
09:00–09:30 MIC Overview (Xeon Phi Coprocessor)
09:30–10:30 Hybrid Computing
10:45-12:00 Lab 4 (Hybrid)
13:00-14:00 Optimization & Scalability
14:00-15:00 Lab 5(Optimization)
15:15-16:30 Profiling & Debugging
Previous Session Content
May 1-2, 2014: Parallel Computing on Stampede Slides and Labs