Parallel Computing on Stampede - March 12 and 13, 2015

9:00 a.m. to 5 p.m. CT, both days
J.J. Pickle Research Campus
ROC 1.900
10100 Burnet Rd
Austin, TX

The Stampede supercomputer at the Texas Advanced Computing Center went into production in January 2013 and was the first system to deploy at scale the Intel Xeon Phi CoProcessor.  Stampede provides nearly 10 petaflops (PF) of peak performance and is the flagship system of the National Science Foundation's XSEDE program.  Stampede provides more than 100,000 cores and 2PF of Intel Xeon E5 "Sandy Bridge" processors and an additional 7+ PF of Intel Xeon Phi coprocessors.

In this tutorial, we will introduce the Stampede architecture, describe the user environment, and discuss optimization techniques for both conventional processors as well as the Xeon Phi coprocessors.

Topics will include:

  •     Stampede architecture overview
  •     Stampede user environment, including the batch system, compiler environment, application modules, etc.
  •     MPI and OpenMP parallel programming
  •     Hands-on exercises on Stampede.
  •     Basic optimization and vector tuning on Stampede  for Sandy Bridge and Xeon Phi Coprocessors (MICs)
  •     Hybrid computing
  •     Intel Xeon Phi Coprocessor (MIC) overview
  •     Programming models for Sandy Bridge - MIC computing: native, symmetric and offload.

Webcast Day 1:

Webcast Day 2:

Link to Chat:

Agenda and Slides:

Day 1   
Welcome and Introductory Remarks   9:00 AM CT 
TACC Systems Review      9:15 AM CT
Break   10:15 AM CT
Introduction to Parallel Computing 10:30 AM CT
Lunch     11:30 AM CT
Linux User Environment  12:30 PM CT
Lab 1:30 PM CT
Break 2:00 PM CT
MPI Programming     2:15 PM CT
Lab - Fortran   C 3:45 PM CT
Day 2   
OpenMP Programming  9:00 AM CT
 Lab 10:00 AM CT
Break 10:30 AM CT
Hybrid Computing 10:45 AM CT
Lunch 11:30 AM CT
Hybrid Computing 12:30 PM CT
Lab 1:15 PM CT
Break 2:00 PM CT
Optimization & Scalability  2:15 PM CT
 Lab  3:15 PM CT
Profiling, Debugging, and Lab 3:45 PM CT



Jason Allison
Advanced Scientific Computing
Senior Program Coordinator